1) Field of the Invention
The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more specifically, to a thin film transistor substrate having a thin film transistor using a polycrystalline silicon film for an active layer and a method of manufacturing the same.
2) Description of the Prior Art
A liquid crystal display panel has advantages of being thin, light weight, and capable of being driven at a low voltage to consume low power, and is therefore widely used in various electronics. In particular, an active matrix liquid crystal panel, in which a switching element such as a thin film transistor (TFT) element is provided for each pixel, is as excellent as a cathode-ray tube (CRT) in display quality. Accordingly, the active matrix liquid crystal panel is used for a display of a portable television, a personal computer or the like.
A twisted nematic (TN) type liquid crystal display panel generally has a structure in which liquid crystal is filled between two transparent glass substrates. Of two surfaces (opposite surfaces) of the glass substrates, which are opposite to each other, on one surface, a black matrix, a color filter, a common electrode and the like are formed. Moreover, on the other surface, a TFT element, a pixel electrode and the like are formed. Furthermore, on surfaces reverse to the opposite surfaces of the glass substrates, polarizing plates are attached, respectively.
The two polarizing plates are arranged so that polarizing axes thereof are perpendicular to each other for example, and thus the liquid crystal display panel operates in a mode in which light is transmitted therethrough without an electric field applied thereto and is shielded with an electric field applied thereto, that is, a normally white mode. Meanwhile, when the polarizing axes of the two polarizing plates are parallel to each other, the liquid crystal display panel operates in a mode in which light is shielded without an electric field applied thereto and is transmitted therethrough with an electric field applied thereto, that is, a normally black mode.
Incidentally, in recent years, a polycrystalline silicon (polysilicon) TFT tends to be used instead of an amorphous silicon TFT. Since current carriers in an amorphous silicon TFT have low mobility, it is required that a driver IC for driving pixel electrodes be separately prepared and connected to a TFT substrate. On the other hand, since current carriers in a polysilicon TFT have high mobility, a driver IC can be formed integrally with TFTs for pixels on the TFT substrate. Accordingly, there is an advantage in that a necessity of separately preparing a driver IC is eliminated to make it possible to reduce cost of the liquid crystal panel and the like.
(A Method of Manufacturing a Polysilicon TFT Substrate According to the Prior Art (1))
FIGS. 1A to 1E are cross sectional views showing a method of manufacturing a polysilicon TFT substrate according to a prior art (1). As shown in FIG. 1A, in the method of manufacturing a polysilicon TFT substrate according to the prior art (1), to begin with, a silicon nitride film (a SiN film) 102 with a thickness of 50 nm and a silicon oxide film (a SiO2 film) 104 with a thickness of about 100 nm are sequentially deposited from bottom to top on a transparent insulating substrate 100 made of a material such as glass to form a buffer layer 106. Note that the SiN film 102 functions as a blocking film to prevent diffusion of impurities into a TFT from the transparent insulating substrate 100.
Next, a semiconductor layer such as a polysilicon film is deposited on the buffer layer 106, and then the semiconductor layer is patterned into an island shape by photo etching, thus forming a semiconductor layer pattern 108 (mask process (1)).
Next, as shown in FIG. 1B, a SiO2 film and an aluminum film (an Al film) are sequentially formed from bottom to top on the semiconductor layer pattern 108 and the buffer layer 106. Subsequently, the SiO2 film and the Al film are patterned by photo etching, thus forming a gate insulating film 110, a gate electrode 112 and a gate busline 112a (mask process (2)).
Next, as shown in FIG. 1C, P+ (phosphorous) ions are implanted into the semiconductor layer pattern 108 by use of the gate electrode 112 as a mask, thereby forming a source region 108a and a drain region 108b of an N channel TFT.
When a peripheral circuit such as a driver is formed of CMOS circuits integrally on the transparent insulating substrate 100, to begin with, P+ ions are implanted into the entire surface of the transparent insulating substrate 100 to form source regions and drain regions of N channel TFTs. Subsequently, regions where the N channel TFTs for pixels and a peripheral circuit are to be formed are covered with a mask such as a resist film, and then impurities such as B+ (boron) ions are selectively implanted into regions where P channel TFTs of the peripheral circuit are to be formed at a dose two or more times as high as a dose of the P+ ions. In such a manner, source regions and drain regions of the N channel TFTs and the P channel TFTs are formed (mask process (2a)).
Next, as shown in FIG. 1D, an interlayer insulating film 116 made of a SiO2 film with a thickness of 300 nm is formed on the gate electrode 112, gate busline 112a and the semiconductor layer pattern 108. Subsequently, the interlayer insulating film 116 is provided with openings on the source region 108a, the drain region 108b and the gate busline 112a by photo etching, thus forming contact holes 116a (mask process (3)).
Subsequently, a molybdenum (Mo) film with a thickness of 300 nm is deposited on the interlayer insulating film 116, and then the Mo film is patterned by photo etching, thereby forming interconnection electrodes 118 (mask process (4)). In this way, the interconnection electrodes 118 are respectively connected to the source region 108a and the drain region 108b of the semiconductor layer pattern 108, and to the gate busline 112a. 
Next, as shown in FIG. 1E, a passivation film 120 made of a silicon nitride (SiN) film with a thickness of 300 nm is formed, and then the passivation film 120 is provided with openings on the interconnection electrodes 118 connected to the source region 108a and the gate busline 112a, thus forming second contact holes 120a (mask process (5)). Note that the passivation film 120 functions as a blocking film to prevent movable ions such as Na ions penetrating from an outside from diffusing into the TFT.
Next, an ITO (indium tin oxide) film is deposited on the passivation film 120, and then the ITO film is patterned by photo etching, thus forming a pixel electrode 122 electrically connected to the source region 108a through the interconnection electrode 118 (mask process (6)). Simultaneously with the foregoing, an ITO film 122a of the same layer as that of the pixel electrode 122 is formed on the interconnection electrode 118 connected to the gate busline 112a. 
As described above, in order to manufacture a conventional polysilicon TFT substrate, when only N channel TFTs are formed, at least six mask processes are required. Meanwhile, when CMOS circuits are formed, at least seven mask processes are required. Note that each mask process includes eight subprocesses as follows: 1) substrate cleaning; 2) photo resist coating; 3) drying; 4) exposure; 5) development; 6) baking; 7) thin film etching or impurity ion implantation; and 8) resist removal.
(A Method of Manufacturing a Polysilicon TFT Substrate According to the Prior Art (2))
FIGS. 2A to 2I are cross sectional views showing a method of manufacturing a polysilicon TFT substrate according to a prior art (2). The method of manufacturing a polysilicon TFT substrate according to the prior art (2) relates to a method of manufacturing a TFT substrate in which a pixel TFT has a light doped drain (LDD) structure in order to suppress an off state current and a peripheral circuit is composed of CMOS TFTs in order to lower electric power consumption.
In the method of manufacturing a polysilicon TFT substrate according to the prior art (2), as shown in FIG. 2A, to begin with, a SiN underlayer 202 and a SiO2 underlayer 204 are sequentially formed from bottom to top on a transparent insulating substrate 200. Subsequently, an amorphous silicon (a-Si) film is deposited on the SiO2 underlayer 204, and then the a-Si film is crystallized by laser and converted into a polysilicon (p-Si) film. Next, a resist film 208 is patterned on the p-Si film, and then the p-Si film is etched by use of the resist film 208 as a mask, thus forming island shaped p-Si film patterns 206 (mask process (1)).
Next, as shown in FIG. 2B, after removing the resist film 208, a gate insulating film and a first conductive film are sequentially formed from bottom to top on the p-Si film patterns 206 and the SiO2 underlayer 204. Subsequently, a resist film 208a for delimiting gate electrodes is patterned on the first conductive film, and then the first conductive film and the gate insulating film are etched by use of the resist film as a mask, thus obtaining the gate electrode 212 and the gate insulating film 210 (mask process (2)). In this event, the gate electrode 212 is formed so as to be narrower than a width of the gate insulating film 210 due to side etching.
Next, as shown in FIG. 2C, a resist film 208b is patterned on a region for a P channel TFT, and then P+ ions are selectively implanted into a region in which an N channel TFT is to be formed with an ion doping system by use of the resist film 208b as a mask. In this event, P+ ion implantation is performed by use of the gate electrode 212 and the gate insulating film 210 as a mask under a doping condition in which accelerating energy is low, thus forming high concentration impurity regions (n+ layer) in portions of the p-Si film pattern 206 which are outside both edges of the gate insulating film 210.
Subsequently, P+ ion implantation is performed through the gate insulating film 210 with an ion doping system by use of the gate electrode as a mask under a condition in which accelerating energy is high, thereby forming low concentration impurity regions (n− layer) in portions of the p-Si film pattern 206 which are outside both edges of the gate electrode 212 and directly under the gate insulating film 210. In this way, a source region 206a and a drain region 206b of the N channel TFT are formed, and an LDD structure of the N channel TFT, in which an n− layer is provided between a channel and the drain region 206b, is also formed.
Next, after removing the resist film 208b, as shown in FIG. 2D, the region for the N channel TFT is masked with a resist film 208c, and then B+ ion doping is performed with an ion doping system (mask process (4)).
In this event, B+ion implantation is performed by use of the gate electrode 212 and the gate insulating film 210 as a mask under a condition in which accelerating energy is low, thereby forming high concentration impurity regions (p+ layer) in portions of the p-Si film pattern 206 which are outside both edges of the gate insulating film 210. Subsequently, B+ ion implantation is performed through the gate insulating film 210 by use of the gate electrode as a mask under a doping condition in which accelerating energy is high, thereby forming low concentration impurity regions (p− layer) in portions of the p-Si film pattern 206 which are outside both edges of the gate electrode 212 and directly under the gate insulating film 210. In this way, a source region 206c and a drain region 206d of the P channel TFT are formed, and an LDD structure of the P channel TFT is also formed.
Next, as shown in FIG. 2E, the B+ ions and the P+ ions, which are implanted into the p-Si film patterns 206, are activated by irradiating excimer laser or the like.
After performing the activation of impurities, as shown in FIG. 2F, a SiO2 film 210a and a SiN film 210b are sequentially deposited from bottom to top to form a first interlayer insulating film 210. Subsequently, a resist film 208d is patterned on the first interlayer insulating film 210, and then the first interlayer insulating film 210 is provided with openings on the source region 206a and the drain region 206b of the N channel TFT and the source region 206c and the drain region 206d of the P channel TFT by etching using the resist film 208d as a mask, thus forming first contact holes 211 (mask process (5)).
Next, as shown in FIG. 2G, a second conductive film is deposited on the first interlayer insulating film 210, a resist film 208e is patterned on the second conductive film, and the second conductive film is etched by use of the resist film 208e as a mask, thus forming interconnection electrodes 212 (mask process (6)).
Next, after removing the resist film 208d, as shown in FIG. 2H, a second interlayer insulating film 214 is deposited, and the second interlayer insulating film 214 is patterned on the source region 206a of the N channel TFT, thus forming a second contact hole 214a (mask process (7)).
Next, as shown in FIG. 2I, an ITO film is deposited on the second interlayer insulating film 214, and then the ITO film is patterned by photo etching, thereby forming a pixel electrode 216 electrically connected to the source region 206a of the N channel TFT through the interconnection electrode 212 (mask process (8)).
As described above, in the method of manufacturing a polysilicon TFT substrate according to the prior art (2), at least eight mask processes are required.
(A Method of Manufacturing a Polysilicon TFT Substrate According to a Prior Art (3)).
FIGS. 3A and 3B are cross sectional views showing the method of manufacturing a polysilicon TFT substrate according to the prior art (3). In the method of manufacturing a polysilicon TFT substrate according to the prior art (3), the number of mask processes is reduced by one using counter doping as compared to the above-described prior art (2).
To begin with, by a method similar to the method of manufacturing a polysilicon TFT substrate of the prior art (2), the same structure as that of FIG. 2B is obtained. Next, after removing a resist film 208a, as shown in FIG. 3A, with an ion doping system, P+ ions are implanted into the entire surface of a transparent insulating substrate 200 without patterning a resist film. In this event, by a method similar to the method of manufacturing a polysilicon TFT substrate of the prior art (2), a source region 206a and a drain region 206b of an N channel TFT having an LDD structure are formed. Simultaneously with the foregoing, P+ ions are implanted also into a p-Si film pattern 206 of a region for a P channel TFT, and a conductivity type of the implanted region is made to be n-type.
Next, as shown in FIG. 3B, a region for the N channel TFT is masked with a resist film 208f, and then B+ ions are implanted into the region for the P channel TFT at a dose two or more times as high as a dose of the above-described P+ ions, thereby converting a conductivity type of the n-type p-Si film pattern 206 into p-type. Thus, a source region 206c and a drain region 206d of the P channel TFT are formed. In this event, B+ ion implantation is performed under an ion doping condition in which an LDD structure is formed also in the P channel TFT.
Next, after removing the resist film 208f, a polysilicon TFT substrate is manufactured by a method similar to the above-described method of manufacturing a polysilicon TFT substrate according to the prior art (2).
In the above-described method of manufacturing a polysilicon TFT substrate according to the prior art (1), at least six mask processes are required. With an increase in the number of mask processes, the number of fabrication processes is inevitably increased. Accordingly, enormous equipment investment is required, thus causing an increase in fabrication cost.
Moreover, in order to realize high speed operation by reducing load capacitance of peripheral circuits for driving TFTs for pixels, interlayer capacitance between the gate electrode 112 and the interconnection electrodes 118 is required to be reduced as small as possible.
Furthermore, an aperture ratio tends to be smaller owing to the fact that a liquid crystal display panel comes to have higher resolution. Therefore, an image on the liquid crystal display panel tends to become darker. As a countermeasure to the foregoing, a so-called bus line light shielding method is used. In the bus line light shielding method, pixel electrodes are extended above data bus lines and gate bus lines, which delimit pixels, and regions between the pixels are shielded by the bus lines. FIG. 4 is a cross sectional view showing an example of the bus line light shielding.
As shown in FIG. 4, in a cross section structure of a portion including a polysilicon TFT element 119 in the bus line light shielding method, a buffer layer 106 is formed on a glass substrate 100, and a p-Si film 108 is formed on the buffer layer 106. Moreover, a gate electrode (a gate bus line) 112 is formed on the p-Si film 108 interposing a gate insulating film 110 therebetween.
The polysilicon TFT 119 is thus composed, and a source region 119a of the polysilicon TFT 119 is connected to a interconnection electrode 118 formed of the same layer as that of a data bus line 118 through a second contact hole 121b formed in an interlayer insulating film 116. Moreover, a data bus line 118 is formed so as to extend on the gate electrode 112 interposing the interlayer insulating film 116 therebetween.
A passivation film 120 is formed on the data bus line 118, and a pixel electrode 122 connected to the interconnection electrode 118 through a third contact hole 120a formed in the passivation film 120 is formed. The pixel electrode 122 is formed so as to extend a position overlapping the gate electrode 112 and the data bus line 118. In this way, light shielding is heretofore performed by using the gate bus line 112 or the data bus line 118.
In a light shielding method in which a CF (color filter) substrate is provided with a black matrix, a deviation between a TFT substrate and the CF substrate due to mask alignment deviation needs to be considered in a range about 3 to 5 μm. On the other hand, in the bus line light shielding method, since it is enough to consider only mask alignment deviation of the TFT substrate, the mask alignment errors can be made as small as 1 to 2 μm. Accordingly, an aperture ratio of the liquid crystal display panel becomes high, making it possible to obtain high contrast images.
In the bus line light shielding method, the pixel electrode and either the gate bus line 112 or the data bus line 118 is required to be formed with sandwiching the interlayer insulating film 116 and the passivation film 120. Therefore, parasitic capacitance therebetween tends to become large. Accordingly, by reducing the parasitic capacitance, coupling between the pixel and both the bus lines 112 and 118 is required to be reduced. Therefore, it is preferred that dielectric constants of the interlayer insulating film 116 and the passivation film 120 be reduced and thicknesses thereof be thickened.
The interlayer insulating film 116 and the passivation film 120 are respectively made of an SiO2 film (dielectric constant: about 3.9) and a SiN film (dielectric constant: about 7), and the dielectric constant of the SiN film is considerably high. The passivation film 120 (the SiN film) is required to be used in order to block penetration of movable ions such as Na.
For example, in order to achieve interlayer capacitance equivalent to that of the SiO2 film (thickness: 300 nm), a film stack structure of the SiO2 film (thickness: 130 nm) and the SiN film (thickness: 300 nm) is required, and therefore the total thickness of the interlayer films becomes as thick as 430 nm.
In order to cope with a state in which interlayer capacitance is further lowered, the interlayer films, which are the interlayer insulating film 116 and the passivation film 120, are required to be thickened. However, when the interlayer insulating film 116 and the passivation film 120 are thickened, there arises a problem that step coverage of the interconnection electrode (the data bus line) 118 is deteriorated in the contact hole, and consequently, a contact failure tends to occur.
In the above-described method of manufacturing a polysilicon TFT substrate according to the prior art (2), eight mask processes are required to form a polysilicon TFT having an LDD structure. Accordingly, the number of fabrication processes is increased as similar to the method of manufacturing a polysilicon TFT substrate according to the prior art (1). Consequently, enormous equipment investment is required, thus causing an increase in fabrication cost.
In addition, in a mask process with ion implantation, since an altered layer is formed on a surface portion of resist, the resist cannot be removed only with a removal solution. Therefore, it is required to perform resist removal in combination with dry ashing, resulting in a problem of a decline of productivity.
In the above-described method of manufacturing a polysilicon TFT substrate according to the prior art (3), since the counter doping method is used for manufacturing CMOS TFTs, an ion implantation process for inverting a conductivity type from n-type to p-type is required. In the ion implantation process, a region for a N channel TFT is covered with a resist mask, and then p-type impurities are implanted into a region for a P channel TFT at a dose two or more times as high as a dose in a conventional method to invert a conductivity type from n-type to p-type. Accordingly, ion implantation takes a lot of time, thereby causing a decline of productivity.
Moreover, in the ion implantation process, impurities are implanted also into the resist mask at a dose two or more times as high as a dose in a typical method. Therefore, an altered layer, which is further difficult to remove, is formed on a surface portion of the resist film. Accordingly, dry ashing takes a lot of time, thereby causing a decline of productivity.
Note that Japanese Unexamined Patent Publication No. Hei6(1994)-59279 discloses a method in which a resist film is not used as a mask for ion implantation, because a resist film is altered by ion implantation and removal of the resist film becomes difficult. However, no consideration is given to improving productivity by forming an LDD structure without an increase in the number of mask processes and the like.